General purpose input/output (GPIO) enables an integrated circuit designer to provide generic pins that may be customized for particular applications. For example, a GPIO pin is programmable to be either an output or an input pin depending upon a user's needs. A GPIO module or peripheral will typically control groups of pins which can vary based on the interface requirement. Because of the programmability of GPIO pins, they are commonly included in microprocessor and microcontroller applications. For example, an applications processor in mobile devices may use a number of GPIO pins to conduct handshake signaling such as inter-processor communication (IPC) with a modem processor.
With regard to such handshake signaling, a sideband signal is deemed as “symmetric” if it must be both transmitted and received by a processor. If there are n symmetric sideband signals that need to be exchanged, each processor requires n*2 GPIO terminals (one GPIO terminal to transmit a given signal and one GPIO terminal to receive that signal). For example, a symmetric IPC interface between a modem processor and an application processor may comprise five signals, which translates to 10 GPIO pins being necessary for the resulting IPC signaling. The need for so many GPIO pins for IPC communication increases manufacturing cost. Moreover, devoting too many GPIO pins for IPC limits the GPIO availability for other system-level peripheral interfaces. The problem cannot be solved by moving the 1PC communication onto the main data bus between the processors in that certain corner conditions may then be violated.
To alleviate the pin demands suffered by conventional GPIO systems, a “virtual” GPIO architecture has been developed in which multiple GPIO signals are serialized onto a single transmit pin such as through a finite state machine (FSM). The FSM receives the multiple GPIO signals from a hybrid GPIO interface that in turn receives the multiple GPIO signals from a processor. The GPIO interface is deemed to be a “hybrid” GPIO because it also interfaces with conventional GPIO pins that transmit conventional GPIO signals. The distinction between the conventional GPIO signals and the virtual GPIO signals carried on the dedicated transmit pin is transparent to the processor. This is quite advantageous in that the processor needs no software modification to communicate through the hybrid GPIO interface. With regard to transmission, the processor thus presents a set of GPIO signals to the hybrid GPIO interface. Depending upon the number of conventional GPIO pins available, the hybrid GPIO interface will present a first subset of the GPIO signals to the conventional GPIO pins for conventional GPIO transmission. In contrast, the hybrid GPIO interface presents a remaining subset of the GPIO signals to the FSM, which serializes them and transmits them over the dedicated transmit pin.
The dedicated transmit pin couples through a suitable transmission line such as a circuit board trace to a receiving integrated circuit's dedicated receive pin. The transmitting integrated circuit discussed above thus also includes a dedicated receive pin for receiving transmitted virtual GPIO signals from a remote integrated circuit. The FSM deserializes the received virtual GPIO signals into a first set of received GPIO signals. Similarly, the FSM receives a second set of received GPIO signals through the conventional GPIO pins. The first and second set of received GPIO signals may then be presented to the processor in a conventional fashion. To the processor, it is thus transparent whether a given received GPIO signal was received on the dedicated receive pin as a virtual GPIO signal or over the conventional GPIO signals. The processor thus needs no software modification with regard to transmission or reception.
The virtual GPIO signals are transmitted in frames. In one embodiment, each frame may include one or more bits from each virtual GPIO signal such that the frame length depends upon the number of virtual GPIO signals. As the number of virtual GPIO signals increases, so would the frame length in such embodiments. This increased frame length increases latency with regard to the time needed to transmit each frame. Should a frame need to be retransmitted due to errors, the resulting latency may exceed system requirements.
Accordingly, there is a need in the art for improved error correction techniques for serial interfaces.